Long wavelength VCSEL bottom mirror

ABSTRACT

A vertical cavity surface emitting laser having an InP substrate and a lower mirror stack comprised of a plurality of alternating layers of AlPSb and GaPSb over the InP substrate. An InP spacer is over the lower mirror stack. An active region is over the InP spacer, and a tunnel junction is over the active region. Then a top mirror structure comprised of a low-temperature formed first GaAs buffer layer, a high-temperature formed second GaAs seed layer, an insulating structure having an opening, and a GaAs/Al(Ga)As mirror stack that is grown by lateral epitaxial overgrowth.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to vertical cavity surface emittinglasers. More specifically, it relates to bottom mirrors used in verticalcavity surface emitting lasers.

[0003] 2. Discussion of the Related Art

[0004] Vertical cavity surface emitting lasers (VCSELs) represent arelatively new class of semiconductor lasers. While there are manyvariations of VCSELs, one common characteristic is that they emit lightperpendicular to a wafer's surface. Advantageously, VCSELs can be formedfrom a wide range of material systems to produce specificcharacteristics.

[0005] VCSELs include semiconductor active regions, which can befabricated from a wide range of material systems, distributed Braggreflector (DBR) mirrors, current confinement structures, substrates, andcontacts. Because of their complicated structure, and because of theirmaterial requirements, VCSELs are usually grown using metal-organicchemical vapor deposition (MOCVD).

[0006]FIG. 1 illustrates a typical VCSEL 10. As shown, an n-dopedgallium arsenide (GaAs) substrate 12 has an n-type electrical contact14. An n-doped lower mirror stack 16 (a DBR) is on the GaAs substrate12, and an n-type graded-index lower spacer 18 is disposed over thelower mirror stack 16. An active region 20, usually having a number ofquantum wells, is formed over the lower spacer 18. A p-type graded-indextop spacer 22 is disposed over the active region 20, and a p-type topmirror stack 24 (another DBR) is disposed over the top spacer 22. Overthe top mirror stack 24 is a p-type conduction layer 9, a p-type caplayer 8, and a p-type electrical contact 26.

[0007] Still referring to FIG. 1, the lower spacer 18 and the top spacer22 separate the lower mirror stack 16 from the top mirror stack 24 suchthat an optical cavity is formed. As the optical cavity is resonant atspecific wavelengths, the mirror separation is controlled to resonant ata predetermined wavelength (or at a multiple thereof. At least part ofthe top mirror stack 24 includes an insulating region 40 that providescurrent confinement. The insulating region 40 is usually formed eitherby implanting protons into the top mirror stack 24 or by forming anoxide layer. In any event, the insulating region 40 defines a conductiveannular central opening 42 that forms an electrically conductive paththough the insulating region 40.

[0008] In operation, an external bias causes an electrical current 21 toflow from the p-type electrical contact 26 toward the n-type electricalcontact 14. The insulating region 40 and the conductive central opening42 confine the current 21 such that the current flows through theconductive central opening 42 and into the active region 20. Some of theelectrons in the current 21 are converted into photons in the activeregion 20. Those photons bounce back and forth (resonate) between thelower mirror stack 16 and the top mirror stack 24. While the lowermirror stack 16 and the top mirror stack 24 are very good reflectors,some of the photons leak out as light 23 that travels along an opticalpath. Still referring to FIG. 1, the light 23 passes through the p-typeconduction layer 9, through the p-type cap layer 8, through an aperture30 in the p-type electrical contact 26, and out of the surface of thevertical cavity surface emitting laser 10.

[0009] It should be understood that FIG. 1 illustrates a typical VCSEL,and that numerous variations are possible. For example, the dopings canbe changed (say, by providing a p-type substrate), different materialsystems can be used, operational details can be tuned for maximumperformance, and additional structures, such as tunnel junctions, can beadded. Furthermore, with long wavelengths it is often beneficial toinsert a reversed biased n++/p++ tunnel junction between the top spacer22 and the active region 20, and to change the doping type of the topstructures to n-type. This is because p-doped materials absorb morelight than n-doped materials, and with longer wavelengths the opticalgain become more critical. The tunnel junction converts electrons intoholes, which are then injected into the active region.

[0010] While generally successful, VCSELs have problems. For example, amajor problem in realizing commercial quality long wavelength VCSELs isthe available mirror materials. Long wavelength VCSELs are often basedon InP material systems. For proper lattice matching, an InP-based VCSELusually uses InP/InGaAsP or AlInAs/AlInGaAs mirrors. However, becausethose materials have relatively low refractive index contrasts, 40-50mirror pairs are typically needed to achieve the required highreflectivity. Growing that number of mirror pairs takes a long time,which increases the production costs.

[0011] Other mirror material systems have been tried. For example,“Metamorphic DBR and tunnel-Junction Injection: A CW RT MonolithicLong-Wavelength VCSEL,” IEEE Journal of Selected topics In QuantumElectronics, vol. 5, no. 3, May/June 1999, describes an InP-InGaAsP DBR,a GaAlAsSb-AlAsSb DBR, and a GaAlInSb-AlAsSb DBR. Furthermore, thatarticle describes using a reversed biased n++/p++ tunnel junction forinjecting current into the active layer. While such mirror materialsystems are advantageous, their lattice match, refractive indexcontrast, and thermal conductivity characteristics are not optimal.Additionally, GaAs/Al(Ga) is still considered to form the bestdistributed Bragg reflector mirrors because of its high refractive indexcontrast, high thermal conductivity, and the feasibility of usingoxidation to enable the formation of oxide insulating regions 40. Thus,new long wavelength VCSELS would be beneficial. Even more beneficialwould be new bottom mirror systems for long wavelength VCSELS. Stillmore beneficial would be new bottom mirror systems that enableGaAs/Al(Ga) top mirror systems.

SUMMARY OF THE INVENTION

[0012] Accordingly, the principles of the present invention are directedto new mirror systems for long wavelength VCSELS. Those principlesspecifically provide for new bottom DBR mirror material systems, andVCSELs that use such new DBR bottom mirror systems. Beneficially, theprinciples of the present invention provide for VCSELS that incorporatenew bottom mirror systems and that use GaAs/Al(Ga) top mirror DBRs.

[0013] A bottom mirror according to one aspect of the present inventionprovides for AlPSb/GaPSb DBR mirrors on an InP substrate, beneficiallyn-doped. Then, an n-doped bottom InP spacer is grown on the AlPSb/GaPSbDBR. Beneficially, an active region having a plurality of quantum wellsis then grown on the n-doped InP spacer. Beneficially, a reversed biasedtunnel junction is disposed over the active region. An n-doped top InPspacer is beneficially grown on the tunnel junction. Also beneficially,an n-doped GaAs/Al(Ga)As top DBR is grown on the n-doped top InP spacer.

[0014] Preferably, the GaAs/Al(Ga)As top DBR is grown by a multi-stepprocess using MOCVD. First, the growth temperature is set to 400-450° C.Then, a 20-40 nanometer thick low temperature GaAs layer is grown on then-doped top InP spacer. After that, the temperature is increased toaround 600° C. A high temperature GaAs seed layer, about 100 nm thick,is then grown on the low temperature GaAs layer. Then an insulationlayer comprised of SiO₂ or Si₂N₄ is formed on the GaAs seed layer. Theinsulation layer is patterned to form an opening. A high temperatureGaAs layer is then grown on the GaAs seed layer, followed by aGaAs/Al(Ga)As top DBR. The high temperature GaAs layer and theGaAs/Al(Ga)As mirror are beneficially grown using lateral epitaxialovergrowth.

[0015] According to another aspect of the present invention, a bottomAlPSb/GaPSb DBR is grown on an n-doped InP substrate. Then, an n-dopedbottom InP spacer is grown on the grown on the AlPSb/GaPSb DBR.Beneficially, an active region having a plurality of quantum wells isthen grown on the n-doped InP spacer, followed by a reversed biasedn++/p++ tunnel junction over the active region. An n-doped top InPspacer is beneficially grown on the tunnel junction. Also beneficially,an n-doped GaAs/Al(Ga)As top DBR is grown on the n-doped top InP spacer.

[0016] Preferably, the GaAs/Al(Ga)As top DBR is grown by a multi-stepprocess using MOCVD. First, the growth temperature is set to 400-450° C.Then, a 20-40 nanometer thick low temperature GaAs layer is grown on then-doped top InP spacer. After that, the temperature is increased toaround 600° C. A high temperature GaAs seed layer, about 100 nm thick,is then grown on the low temperature GaAs layer. Then, an insulationlayer comprised of SiO₂ or Si₂N₄ is formed on the GaAs seed layer. Thatinsulation layer is then patterned to form an opening. A hightemperature GaAs layer is then grown on the GaAs seed layer. Then, aGaAs/Al(Ga)As top DBR is grown on the high temperature GaAs layer. TheGaAs layer and the GaAs/Al(Ga)As mirror are beneficially grown usinglateral epitaxial overgrowth.

[0017] Additional features and advantages of the invention will be setforth in the description that follows, and in part will be apparent fromthat description, or may be learned by practice of the invention.

BRIEF DESCRIPTION OF THE DRAWING

[0018] The accompanying drawings, which are included to provide afurther understanding of the invention and which are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and together with the description serve to explain theprinciples of the invention.

[0019] In the drawings:

[0020]FIG. 1 illustrates a typical vertical cavity surface emittinglaser;

[0021]FIG. 2 illustrates a first embodiment vertical cavity surfaceemitting laser that is in accord with the principles of the presentinvention;

[0022]FIG. 3 illustrates an intermediate structure during fabrication ofthe vertical cavity surface emitting laser illustrated in FIG. 2;

[0023]FIG. 4 illustrates another intermediate structure duringfabrication of the vertical cavity surface emitting laser illustrated inFIG. 2;

[0024]FIG. 5 illustrates yet another intermediate structure duringfabrication of the vertical cavity surface emitting laser illustrated inFIG. 2; and

[0025]FIG. 6 illustrates a second embodiment vertical cavity surfaceemitting laser that is in accord with the principles of the presentinvention.

[0026] Note that in the drawings that like numbers designate likeelements. Additionally, for explanatory convenience the descriptions usedirectional signals such as up and down, top and bottom, and lower andupper. Such signals, which are derived from the relative positions ofthe elements illustrated in the drawings, are meant to aid theunderstanding of the present invention, not to limit it.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0027] The principles of the present invention are incorporated in afirst embodiment VCSEL having a bottom AlPSb/GaPSb DBR mirror grown onan InP substrate. An example of such a VCSEL is the VCSEL 100illustrated in FIG. 2.

[0028] As shown in FIG. 2, the VCSEL 100 includes an n-doped InPsubstrate 112 having an n-type electrical contact (not shown forclarity). Over the InP substrate 112 is an n-doped lower mirror stack116 (a DBR) comprised of a plurality of alternating layers ofAlPSb/GaPSb. Over the lower mirror stack 116 is an n-doped InP spacer118. The lower mirror stack 116 is beneficially grown on the InPsubstrate using TMAl, TMSb, and PH₃ in an MOCVD process. Then, the InPspacer 118 is grown, also using MOCVD. An active region 120 comprised ofP-N junction structures and a large number of quantum wells is thenformed over the InP spacer 118. The composition of the active region 120is beneficially AlInGaAs or InGaAsP.

[0029] Over the active region 120 is a tunnel junction 122 comprised ofa reverse biased n++/p++ junction. Beneficially, the tunnel junctionincludes a p-layer comprised of MOCVD-grown GaAs_((1-x))Sb_(x). DuringMOVCD, TMGa (or TEGa), TMSb, and AsH₃ (or TBAs) are beneficially used toproduce the GaAs_((1-x))Sb_(x) layer. Beneficially, that layer's solidcomposition is controlled by controlling the ratio of As to Sb. TheMOCVD growth temperature is between 500° C. and 650° C. Doping isbeneficially performed using CCl₄ or CBr₄ such that the resultingp-doping is greater 1×10¹⁹ cm⁻³. In practice, a p-doping greater than5×10¹⁹ cm⁻³ is beneficial. It should be noted that theGaAs_((1-x))Sb_(x) layer can have a doping as high as 1×10²⁰ cm⁻³without annealing. By setting x=0.5 a tunnel junction that is latticematched to InP is produced (but GaAs_((0.5))Sb_(0.5) has a bandgap of0.71 eV at 300K). An alternative is to set x=0.4, 0.3, or 0.23, whichproduce GaAs_((1-x))Sb_(x) layers with bandgaps of 0.8 eV, 0.91 eV, or 1eV, but which are not lattice matched to the InP active region 120. Atx=0.3, or 0.23 the strains respectively become 1.4% or 1.95%, which,while not ideal, are much better than the 3.55% strain of AlAs on InP.

[0030] The tunnel junction 122 further includes an n-doped layer of InP,AlInAs, or of a lower bandgap material such as AlInGaAs or InGaAsP. Then-doped layer should also be heavily doped (greater than 5×10¹⁹ cm⁻³)and very thin (less than about 10 nanometers). For good latticematching, the VCSEL 100 uses an InP n-type layer in the tunnel junction122.

[0031] Over the tunnel junction 122 is an n-type InP top spacer 124.Then, a top mirror structure (which includes another DBR) is disposedover the top spacer 124.

[0032] The top mirror structure is beneficially comprised of a lowtemperature grown GaAs buffer layer 126 over the top spacer 124, a hightemperature GaAs buffer layer 128 (which acts as a seed layer) over theGaAs buffer layer 126, an insulating structure (beneficially comprisedof SiO₂) 130 over most of the GaAs buffer layer 128, and a GaAs/Al(Ga)Asmirror stack 132 over the insulating structure 130. A shown, theinsulating structure includes an opening 131, which enables current flowthrough the VCSEL 100.

[0033] The top mirror structure implements a device qualityGaAs/Al(Ga)As mirror stack 132 over the top spacer 124. In manyapplications, GaAs/Al(Ga)As is considered the best material for Braggmirrors because of its high refractive index contrast(GaAs:AlAs=3.377:2.893), high thermal conductivity (GaAs:AlAs=0.46:0.8),and its oxidation potential. However, GaAs/Al(Ga)As is seriously latticemismatched with InP. Thus, to produce a device-quality GaAs/Al(Ga)Asmirror stack, MOCVD is used in a two-step process to form intermediateGaAs buffer layers.

[0034]FIG. 3 illustrates the first step of the two-step process. A lowtemperature GaAs buffer layer 126 is formed over the InP spacer 124. Thelow temperature GaAs buffer layer 126 is produced by adjusting the MOCVDgrowth temperature to about 400-450° C., and then MOCVD growing the lowtemperature GaAs buffer layer 126 to a thickness of about 20-40 nm.

[0035] Referring now to FIG. 4, after the low temperature GaAs bufferlayer 126 is formed, the temperature is increased to around 600° C.Then, the high temperature GaAs buffer layer 128 is grown. The GaAsbuffer layer 128 acts as a seed layer for subsequent growths.

[0036] Referring now to FIG. 5, after the GaAs buffer layer 128 isgrown, a dielectric layer of SiO₂ (alternatively of Si₃N₄) is depositedand patterned to form the insulating structure 130. To do so, theintermediate structure shown in FIG. 4 is removed from the MOCVD reactorvessel. Then, a dielectric layer of SiO₂ (alternatively Si₃N₄) isdeposited on the insulating structure 130. Then, the depositeddielectric layer is patterned to produce the insulating structure 130having the opening 131. The insulating structure 130 provides a suitablesurface for lateral epitaxial overgrowth. After the insulating structure130 formed, the intermediate structure of FIG. 5 is inserted into theMOCVD reactor vessel. Referring once again to FIG. 2, the GaAs/Al(Ga)Asmirror stack 132 is then grown by MOCVD. That mirror stack is producedby lateral epitaxial overgrowth from the GaAs buffer layer 128 throughthe opening 131. The result is a high-quality mirror stack 132 havingcurrent confinement.

[0037] With the mirror stack 132 formed, an n-type conduction layer(similar to the p-type conduction layer 9 of FIG. 1), an n-type GaAs caplayer (similar to the p-type GaAs cap layer 8 of FIG. 1), and an n-typeelectrical contact (similar to the p-type electrical contact 26 ofFIG. 1) are produced.

[0038] An alternative embodiment VCSEL 200 that is in accord with theprinciples of the present invention is illustrated in FIG. 6. The VCSEL200 includes an n-doped InP substrate 212 having an n-type electricalcontact (which is not shown for clarity). Over the InP substrate 222 isn-doped lower mirror stack 216 (a DBR) comprised of a plurality ofalternating layers of AlGaInAs and AlInAs. Over the lower mirror stack216 is an InP spacer 218. The lower mirror stack 216 is beneficiallygrown on the InP substrate using TMAl, TMSb, and PH₃ in an MOCVDprocess. Then, the InP spacer 218 is grown, also using MOCVD.

[0039] An active region 220 comprised of P-N junction structures and alarge number of quantum wells are then formed over the InP spacer 218.The composition of the active region 220 is beneficially InP. Over theactive region 220 is a tunnel junction 222 comprised of a reverse biasedn++p++ junction. Beneficially, the tunnel junction 22 is as describedabove (and thus includes a MOCVD-grown GaAs_((1-x))Sb_(x) layer).

[0040] Over the tunnel junction 222 is an n-type InP top spacer 224.Then, a top mirror structure (which includes another DBR) is disposedover the top spacer 224. The top mirror structure is beneficiallycomprised of a low temperature GaAs buffer layer 226 over the top spacer224, a high temperature GaAs buffer layer 228 over the GaAs buffer layer226, an insulating structure (beneficially comprised of SiO₂) 130 overmost of the GaAs buffer layer 228, and a GaAs/AI(Ga)As mirror stack 232over the insulating structure 230. Beneficially, the top mirrorstructure is fabricated in the same manner as the top mirror structureof FIG. 2 (as discussed with regard to FIGS. 3-5).

[0041] With the mirror stack 232 formed, an n-type conduction layer(similar to the p-type conduction layer 9 of FIG. 1), an n-type GaAs caplayer (similar to the p-type GaAs cap layer 8 of FIG. 1), and an n-typeelectrical contact (similar to the p-type electrical contact 26 ofFIG. 1) are produced.

[0042] The VCSELs 100 and 200 have significant advantages over prior artlong wavelength InP VCSELs. First, the two-step MOCVD process enables adevice quality GaAs/Al(Ga)As top mirror to be used with an InP activeregion 120 and an InP top spacer 124. Another advantage is that thetunnel junction 122 enables n-doped top layers to be used, which reducesoptical absorption (which can be critically important in long wavelengthVCSELs). Yet another advantage is the avoidance of InP/InGaAsP mirrorstacks, which requires a large numbers of mirror pairs. Consequently, areduction in mirror growth times and costs is possible. Furthermore, themirrors stacks used in the VCSEL 100 and in the VCSEL 200 enableimproved thermal performance. Still another advantage is the ease offorming current confinement in the top mirror structure, and the use oflateral epitaxial overgrowth to produce the top mirror. The overallresult is VCSELs having improved performance, increased reliability,faster fabrication, and reduced cost.

[0043] It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. A vertical cavity surface emitting laser,comprising: an InP substrate; and a lower mirror stack comprised of aplurality of alternating layers of AlPSb and GaPSb over the InPsubstrate.
 2. A vertical cavity surface emitting laser according toclaim 1, wherein the alternating layers of AlPSb and GaPSb are grown byMOCVD.
 3. A vertical cavity surface emitting laser according to claim 1,further including a lower InP spacer over the lower mirror stack.
 4. Avertical cavity surface emitting laser according to claim 3, wherein thelower InP spacer is grown by MOCVD.
 5. A vertical cavity surfaceemitting laser according to claim 3, further including an AlInGaAs or anInGaAsP active region over the InP spacer.
 6. A vertical cavity surfaceemitting laser according to claim 5, further including a tunnel junctionover the active region.
 7. A vertical cavity surface emitting laseraccording to claim 6, wherein the tunnel junction includes anMOCVD-grown GaAs_((1-x))Sb_(x) layer.
 8. A vertical cavity surfaceemitting laser according to claim 6, further including a first GaAsbuffer layer over the tunnel junction, wherein the first GaAs bufferlayer is grown by MOCVD between 400° C. and 450° C.
 9. A vertical cavitysurface emitting laser according to claim 8, further including a secondGaAs seed layer over the first GaAs buffer layer, wherein the secondGaAs seed layer is grown by MOCVD at about 600° C.
 10. A vertical cavitysurface emitting laser according to claim 9, further including aninsulating structure on the second GaAs seed layer, wherein theinsulating structure includes an opening.
 11. A vertical cavity surfaceemitting laser according to claim 10, further including a GaAs/Al(Ga)Asmirror stack on the second GaAs seed layer and on the insulatingstructure, wherein the GaAs/Al(Ga)As mirror stack is grown by lateralepitaxial overgrowth from the second GaAs seed layer.
 12. A verticalcavity surface emitting laser, comprising: an InP substrate; and a lowermirror stack comprised of a plurality of alternating layers of AlGaInAsand AlInAs over the InP substrate.
 13. A vertical cavity surfaceemitting laser according to claim 12, further including a lower InPspacer over the lower mirror stack.
 14. A vertical cavity surfaceemitting laser according to claim 13, wherein the lower InP spacer isgrown by MOCVD.
 15. A vertical cavity surface emitting laser accordingto claim 13, further including an AlInGaAs or InGaAsP active region overthe InP spacer.
 16. A vertical cavity surface emitting laser accordingto claim 15, further including a tunnel junction over the active region.17. A vertical cavity surface emitting laser according to claim 16,wherein the tunnel junction includes a MOCVD-grown GaAs_((1-x))Sb_(x)layer.
 18. A vertical cavity surface emitting laser according to claim16, further including a first GaAs buffer layer over the tunneljunction, wherein the first GaAs buffer layer is grown by MOCVD between400° C. and 450° C., and a second GaAs seed layer over the first GaAsbuffer layer, wherein the second GaAs seed layer is grown by MOCVD atabout 600° C.
 19. A vertical cavity surface emitting laser according toclaim 18, further including an insulating structure on the second GaAsseed layer, wherein the insulating structure includes an opening.
 20. Avertical cavity surface emitting laser according to claim 19, furtherincluding a GaAs/AI(Ga)As mirror stack on the second GaAs seed layer andon the insulating structure, wherein the GaAs/Al(Ga)As mirror stack isgrown by lateral epitaxial overgrowth from the second GaAs seed layer.